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SK10/100E111
HIGH-PER.ORMANCE PRODUCTS HIGH-PER.ORMANCE PRODUCTS Description
The SK10E/100E111 is a low skew 1-to-9 differential driver designed with clock distribution in mind. It accepts one signal input which can be either differential or singleended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q* outputs HIGH. The device is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew withindevice, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 , even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
1:9 Differential Clock Driver
.eatures
* * * * * * * * * * *
PRELIMINARY
Low Skew Guaranteed Skew Spec Differential Design VBB Output Enable Input Extended 100E VEE Range of -4.2 to -5.5V 75K Internal Input Pulldown Resistors Fully Compatible with MC10E111 and MC100E111 Specified Over Industrial Temperature Range: -40 oC to 85oC ESD Protection of >4000V Available in 28-pin PLCC Package
.unctional Block Diagram
Q0 Q0* Q1 Q1* Q2 Q2* Q3 Q3* Q4 Q4* IN IN* Q5 Q5* Q6 Q6* Q7 Q7* Q8 Q8*
EN*
VBB
Revision 1 /.ebruary 13, 2001
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SK10/100E111
HIGH-PER.ORMANCE PRODUCTS PIN Description
Pinout
VCC0 Q1* Q2*
19 18 17 16 Q3 Q3* Q4 VCC0 Q4* Q5 Q5* 15 (Top View) IN* VBB N/C 2 3 4 5 6 7 8 9 10 11 14 13 12
Q0*
Q1
25 VEE EN* IN VCC 26 27 28
24
23
22
21
28 Lead PLCC
1
VCC0
Q8
Q7
Q2
20
Q0
Q8*
Q7*
Pin Names
Pin IN, IN* EN* Q0, Q0* - Q8, Q8* VBB .unction Differential Input Pair Enable Differential Outputs VBB Output
Q6*
Q6
Revision 1 /.ebruary 13, 2001
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SK10/100E111
HIGH-PER.ORMANCE PRODUCTS Package Information
Y BRK -N-
D
PIN Descriptions
-L-
-M-
W
D
V 28 1
A Z R
0.007 (0.180) M T L - M 0.007 (0.180)
M
S S
NS NS
T L-M
C
+ +
E G J G1 0.010 (0.250) S T L - M S N S VIEW S 0.004 (0.100) -T- SEATING PLANE
NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash is 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom by up to 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch betweeen the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension smaller than 0.025 (0.635).
B
0.007 (0.180) U
M
T
L-M
M
S
N
S
INCHES
0.007 (0.180) + Z T L-M
S
MILLIMETERS
MIN 12.32 12.32 4.20 2.29 0.33 MAX 12.57 12.57 4.57 2.79 0.48
N
S
DIM A B C E
MIN 0.485 0.485 0.165 0.090 0.013
MAX 0.495 0.495 0.180 0.110 0.019
+ X G1 0.010 (0.250) S T L-M
S
N
S
. G H J K
0.050 BSC 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 -2o 0.410 0.040 0.032 --0.456 0.456 0.048 0.048 0.056 0.020 10o 0.430 --
1.27 BSC 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 -2o 10.42 1.02 0.81 --11.58 11.58 1.21 1.21 1.42 0.50 10o 10.92 --
H
0.007(0.180) M T L - M S N S
R U V
K1
W X Y
K F 0.007 (0.180) M T L - M
S
Z
N
G1
S
K1
VIEW S
Revision 1 /.ebruary 13, 2001 3 www.semtech.com
SK10/100E111
HIGH-PER.ORMANCE PRODUCTS DC Characteristics
SK10/100E111 DC Electrical Characteristics (Notes 1, 2)
(VCC - VEE = 4.2V to 5.5V; VOUT Loaded 50 to VCC - 2.0V)
TA = -40oC
TA = 0oC
TA = +25oC
TA = +85oC
Symbol V BB IIN I EE
Ch a r a c t e r i s t i c Output Reference Voltage13
10EL 100EL
Min - 1. 43 - 1. 38 - 150
Max - 1. 30 - 1. 26 150 150 64
Min - 1. 38 - 1. 38 - 150
Max - 1. 27 - 1. 26 150 150 64
Min - 1. 35 - 1. 38 - 150
Max - 1. 25 - 1. 26 150 150 64
Min - 1. 31 - 1. 38 - 150
Max - 1. 19 - 1. 26 150 150 64
Un i t V V A A mA
I n p u t Cu r r e n t ( Di f f ) ( SE) Power Supply Cur rent
AC Characteristics
SK10/100E111 AC Electrical Characteristics
(VCC - VEE = 4.2V to 5.5V; VOUT Loaded 50 to VCC - 2.0V)
TA = -40oC
Symbol t PLH t P HL Ch a r a c t e r i s t i c Propagation Delay to Ou t p u t I N ( Di f f ) 5 I N ( SE) 6 Enabl e7 Di s a b l e S e t u p T i me 9 EN t o I N H o l d T i me 1 0 I N t o EN R e l e a s e T i me 1 1 E N* t o I N Within-Device Skew8 Mi n i mu m I n p u t Swi n g 12 C o mmo n Mo d e Range4 Rise/.all Time 20% t o 80% 250 VEE + 1. 6 215 450 Min Typ Max Min
TA = 0oC
Typ Max
TA = +25oC
Min Typ Max
TA = +85oC
Min Typ Max Un i t
475 280 400 400 250 50 350 0 - 200 100 25
630 780 900 900
490 330 450 450 200 0 300 0 - 200 100 25 250 VEE + 1. 6 225 375
655 730 850 850
500 330 450 450 200 0 300 0 - 200 100 25 250 VEE + 1. 6 230 375
660 730 850 850
520 330 450 450 200 0 0 - 200 300
655 730 850 850
ps ps ps ps ps ps
ts tH tR tskew VPP(AC) V C MR tr , tf
100 50 1000 VCC 0. 4
ps ps mV V ps
75 1000 VCC 0. 4 545
50 1000 VCC 0. 4 570
50 1000 VCC 0. 4 545 250 VEE + 1. 6 240
25
375
475
Revision 1 /.ebruary 13, 2001
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SK10/100E111
HIGH-PER.ORMANCE PRODUCTS AC Characteristics (continued)
IN IN* ts 50% EN* Q* Q 75 mV 75 mV
Q* Q 75 mV IN IN* th EN*
IN IN* tr EN*
50% 75 mV
50%
Q* Q
Figure 1. Setup Time
Figure 2. Hold Time
Figure 3. Release Time
Notes: 1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. Differential input voltage required to obtain a full ECL swing on the outputs. 4. VCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between VPP(min) and 1V. The lower end of VCMR range varies 1:1 with VEE and is equal to VEE+1.6V. 5. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 6. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 7. Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the 50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative transition on Q (or a positive transition on Q). 8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 9. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75 mV to that IN/IN transition (see Figure 1). 10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN* to prevent an output response greater than 75 mV to the IN/IN transition (see Figure 2). 11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3). 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 250 mV will still produce full ECL levels at the output. 13. Voltages referenced to VCC = 0V. 14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet. 15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Revision 1 /.ebruary 13, 2001 5 www.semtech.com
SK10/100E111
HIGH-PER.ORMANCE PRODUCTS Ordering Information
Ordering Code SK10E111PJ SK10E111PJT SK100E111PJ SK100E111PJT
Package ID 28-PLCC 28-PLCC 28-PLCC 28-PLCC
Temperature Range Industrial Industrial Industrial Industrial
Contact Information
Division Headquarters 10021 Willow Creek Road San Diego, CA 92131 Phone: (858) 695-1808 FAX: (858) 695-2633
Semtech Corporation High-Performance Products Division
Marketing Group 1111 Comstock Street Santa Clara, CA 95054 Phone: (408) 566-8776 FAX: (408) 727-8994 www.semtech.com
Revision 1 /.ebruary 13, 2001
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